(a) Field of the Invention
The invention relates to a power mesh arrangement method, particular to a power mesh arrangement method applied in an integrated circuit having multiple power domains.
(b) Description of the Related Art
As the circuitry of the integrated circuit becomes more and more complicate, there are possibilities that different portions of the circuitry of a chip need different voltages (powers) at the same time. For example, the chip circuitry may have two kinds of operating modes: the normal operating mode and the sleeping mode. During the normal operating mode, the entire chip circuitry uses the operating voltage for its normal operation. But during the sleeping mode, only part of the chip circuitry needs to be maintained in the normal operating mode. Therefore, the normal operating voltage is still used by these circuits for its operation while the other circuits of the chip only need a lower voltage for maintaining the sleeping mode operation.
Therefore, different powers need to be supplied to the different circuits inside the chip so that the circuits can perform different operations during the sleeping mode. Hence, it is common practices to arrange multiple power domains in the chip circuitry. In other words, circuits in different power domains are coupled to different powers respectively so that the circuits of different power domains use different powers to support the different operations that are just mentioned.
But, the traditional circuit design approach does not provide a simple rule or step for the circuit designer to plan and design the power routing of a circuit having multiple power domains. For example, the well-known automatic placement and routing (APR) tool can only support circuits having single power domain. Therefore, a circuit designer can only rely on the most primitive method to design the power routing of multiple power domains, such as the manual routing. Obviously, such design approach is not only complicated but also inefficient.